1. Field of the Invention
The invention relates to static random access memory (SRAM), and more particularly to SRAM array and cell layouts, layout methods for such memories, and related technologies.
2. Description of Related Art
In most integrated circuit designs, SRAM is a critical component that occupies relatively large area, draws significant power, and determines chip performance. Despite feature size scaling, the minimum channel length in an SRAM cell remains nearly twice as large as that in core logic areas, due to the need to control variability and leakage.
A typical 6-transistor SRAM cell 100 circuit schematic is shown in FIG. 1. It is based on a pair of cross-connected inverters, and includes a first inverter made with a first P-channel pull-up transistor PU1 and a first N-channel pull-down transistor PD1, and a second inverter made with a second P-channel pull-up transistor PU2 and a second N-channel pull-down transistor PD2. The drain of transistor PU1 is connected to the drain of transistor PD1, and the drain of transistor PU2 is connected to the drain of transistor PD2. The sources of both transistors PU1 and PU2 are connected to Vdd and the sources of both transistors PD1 and PD2 are connected to ground. The gates of transistors PU1 and PD1 are connected together and to the node connecting the drain of PU2 with the drain of PD2. Similarly, the gates of transistors PU2 and PD2 are connected together and to the node connecting the drain of PU1 with the drain of PD1. The ‘true’ bit line BL is connected to the gates of transistors PU2 and PD2 through a first pass gate transistor PG1, and the ‘complement’ bit line BLB is connected to the gates of transistors PU1 and PD1 through a second pass gate transistor PG2. As used herein, the terms “true” and “complement” bit lines are used as a convenience to mean opposite polarity bit lines of a differential pair. In a particular array, which bit line is considered “true” and which is considered “complement” depends on circuitry outside the array.
A typical FinFET-based layout of the 6-transistor cell 100 is shown in FIG. 2. The layout diagram shows an N-channel diffusion 210, in which channel regions of transistors PG1 and PD1 are defined by gate electrodes 212 and 214, respectively. Also shown is a P-channel diffusion 216, in which gate electrode 214 defines the channel region of transistor PU1. Also shown is another N-channel diffusion 218, in which channel regions of transistors PD2 and PG2 are defined by gate electrodes 220 and 222, respectively. Also shown is another P-channel diffusion 224, in which gate electrode 220 defines the channel region of transistor PU2. The diffusions 210, 216, 218 and 224 are formed in fins. Local metal interconnect 226 connects the gate electrode 220 to the junction between transistors PG1, PD1 and PU1, and Local interconnect 228 connects the gate electrode 214 to the junction between transistors PG2, PD2 and PU2. Higher level metal interconnects are not shown in FIG. 2, but connections to WL, BL, BLB, Vdd and GND are indicated. In general, unless otherwise stated, for clarity of illustration, such higher level interconnects are not shown in any of the layout drawings herein.
If λ is the minimum pitch for a particular fabrication technology, the width of the gate conductors 212, 214, 220 and 222 (and therefore the channel lengths of all the transistors) may for example be 0.8λ (twice the minimum channel length of 0.4λ). The fin width may be 0.36λ, yielding a total cell area of 36λ2.
For a variety of reasons, integrated circuit features at advanced technology nodes are typically laid out along orthogonal parallel virtual lines. For the gate electrodes, a number of parallel virtual lines are defined to extend across the layout, or at least across the SRAM cell array. These parallel virtual lines are referred to herein as gate electrode tracks or layout tracks, and they are used to index placement of gate electrodes of the transistors within the layout. In the layout of FIG. 2, the six transistors share two gate electrode tracks: electrodes 212 and 220 share a track 230, and electrodes 214 and 222 share a track 232. As feature sizes continue to shrink, it has become very difficult to vary the width of the electrode material sharing a particular track. The difficulty arises in part because of diffraction artifacts caused by sub-wavelength lithography. Thus all the transistors sharing a particular track typically have the same channel length. In the layout of FIG. 2, this means that transistors PG1, PU2 and PD2 all have the same channel length, and transistors PG2, PU1 and PD1 all have the same channel length. In addition, transistor channel widths can be varied only by adding or subtracting fins, a quantized adjustment which precludes continuous transistor width sizing.
In an SRAM cell based on cross-connected inverters, a balance is required between the read and write operations. The feedback within the cell must be weak enough such that a data write operation can flip the stored value, but its output drive current also must be strong enough to charge up the bit lines when selected during a read operation. In older technologies, it was commonplace to adjust the channel lengths and widths of the various transistors in order to achieve device ratios which achieve this balance with optimal static noise margin, leakage, and area. Unfortunately, the SRAM layout of FIG. 2 does not permit such individual transistor sizing.
Aspects of the invention address this problem.